Semiconductor memory module

ABSTRACT

A bare chip includes a first semiconductor storage part and a second semiconductor storage part, formed in the stage of a wafer serving as a semiconductor material, capable of storing data independently of each other, and an electric wire serving as a semiconductor storage part employment/nonemployment selection circuit setting each of the first semiconductor storage part and the second semiconductor storage part in either a mode capable of inputting/outputting data or a mode incapable of inputting/outputting the data. Thus obtained is a semiconductor memory module formed by a plurality of bare chips integrally coated with molding resin, having a function of replacing a bare chip detected as defective with a spare chip.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor memory modulehaving a plurality of semiconductor chips mounted on a module substrate

[0003] 2. Description of the Background Art

[0004] A method of fabricating a conventional semiconductor chip formedby a bare chip singly coated with molding resin is now described. In themethod of fabricating the conventional semiconductor chip, each of barechips 101 formed as parts of a wafer 140 shown in FIG. 5 is subjected toa probe test (wafer test (WT)) after completion of a wafer process.Among the plurality of bare chips 101, a bit detected as defective as aresult of the probe test is replaced with a normally functioning sparebit. Thus, each bare chip 101 is employed as a semiconductor chipnormally functioning as a simple substance.

[0005] Then, the wafer 140 is diced (cut) along dicing lines 112 shownin FIG. 5, for separating the bare chips 101 from each other. A leadframe is die-bonded (fixed) to each bare chip 101 cut out from the dicedwafer 140. As shown in FIG. 6, thin metal bonding wires 105 connectbonding pads 106 of the bare chip 101 and the lead frame with eachother. Thereafter the bare chip 101 and the lead frame are molded(sealed) with resin or ceramic.

[0006] After the aforementioned assembly step, a final test (FT)represented by an acceleration test or an electrical characteristic testis performed in order to check whether or not each bare chip 101normally functions. Finally, a QAT (quality assurance test) isperformed. Consequently, bare chips 101 having excellent quality areshipped as finished products.

[0007] As to the aforementioned semiconductor chip prepared by singlycoating the bare chip 101 with molding resin, therefore, the final testcan be performed when each semiconductor chip is coated with the moldingresin. When a semiconductor memory module is fabricated by mounting aplurality of such semiconductor chips prepared by individually coatingthe bare chips 101 with molding resin on a module substrate, therefore,the semiconductor memory module can be repaired by replacing only asemiconductor chip detected as defective in the final test with anothernormally functioning semiconductor chip (The chip functions without anyproblem in usual use).

[0008] When another type of semiconductor memory module is fabricated bymounting the aforementioned plurality of bare chips 101 on a modulesubstrate and integrally sealing the plurality of bare chips 101 withmolding resin, for example, and at least a single defective bare chip101 is detected in a system test performed after integrally sealing theplurality of bare chips 101, however, it is difficult to replace thedefective bare chip 101 with another normally functioning bare chip 101,and hence the yield is reduced.

[0009] However, the semiconductor memory module fabricated by mountingthe plurality of bare chips 101 on the module substrate and integrallysealing the plurality of bare chips 101 is superior to the semiconductormemory module fabricated by mounting the plurality of semiconductorchips prepared by individually coating the bare chips 101 with themolding resin on the module substrate in a point that the mounting areafor the bare chips 101 can be reduced.

[0010] Therefore, a semiconductor memory module fabricated by mounting aplurality of bare chips 101 on a module substrate and integrally sealingthe plurality of bare chips 101 as shown in FIG. 7 desirably includes aspare bare chip with a function of replacing a bare chip 101 detected asdefective with the spare bare chip.

SUMMARY OF THE INVENTION

[0011] An object of the present invention is to provide a semiconductormemory module, fabricated by integrally sealing a plurality of barechips, having a function of replacing a bare chip detected as defectivewith a spare bare chip.

[0012] The semiconductor memory module according to the presentinvention has a plurality of semiconductor chip assemblies, eachincluding a single plate semiconductor material formed by combining aplurality of semiconductor chips with each other, mounted on a modulesubstrate. Each semiconductor chip assembly includes a plurality ofsemiconductor storage parts provided on the semiconductor material forindividually functioning as the said plurality of semiconductor chipsand a semiconductor storage part employment/nonemployment selectioncircuit setting each of the plurality of semiconductor storage parts ineither a mode capable of inputting/outputting data or a mode incapableof inputting/outputting the data.

[0013] According to the aforementioned structure, a spare semiconductorchip is provided among the plurality of semiconductor chips, so that thesemiconductor memory module can exhibit a prescribed function whether ornot the plurality of semiconductor chips mounted on the module substrateinclude a defective semiconductor chip. Therefore, the yield of thesemiconductor memory module is improved.

[0014] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is a shot layout diagram of a wafer for fabricating barechips forming a semiconductor memory device according to an embodimentof the present invention with dicing lines for dicing the wafer andcutting out the bare chips and regions provided with activity/inactivityselection circuits;

[0016]FIG. 2 illustrates an exemplary bare chip forming thesemiconductor memory device according to the embodiment;

[0017]FIG. 3 is a diagram for illustrating another exemplary bare chipforming the semiconductor memory device according to the embodiment;

[0018]FIG. 4 is a diagram for illustrating the structure of asemiconductor memory module according to the embodiment;

[0019]FIG. 5 illustrates dicing lines in a wafer for fabricating barechips forming a conventional semiconductor memory device;

[0020]FIG. 6 is a diagram for illustrating a bare chip cut out from thewafer by dicing; and

[0021]FIG. 7 illustrates the layout of bare chips in a conventionalsemiconductor memory module.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] A semiconductor memory module and a method of fabricating asemiconductor chip employed therefor according to an embodiment of thepresent invention are now described with reference to FIGS. 1 to 4.

[0023] First, a method of cutting out each bare chip 1 for forming asemiconductor memory device from a semiconductor wafer 40 is describewith reference to FIG. 1.

[0024] As shown in FIG. 1, the semiconductor wafer 40 is diced with agenerally employed dicing machine, for cutting out each bare chip 1forming the semiconductor memory device according to this embodiment.Referring to FIG. 1, one-dot chain lines 12 show dicing lines includinga plurality of lines transversely extending at intervals similar tothose of conventional dicing lines and a plurality of lines verticallyextending at intervals twice those of the conventional dicing lines.Each bare chip 1 cut out along such dicing lines has a firstsemiconductor storage part 1 a and a second semiconductor storage part 1b, which are storage areas capable of storing data independently of eachother. In other words, each of the first and second semiconductorstorage parts 1 a and 1 b singly functions as a semiconductor chip.Therefore, a semiconductor chip assembly including a plate member formedby the first and second semiconductor storage parts 1 a and 1 b includestwo semiconductor chips singly functioning as semiconductor chips, andis different from a semiconductor chip having a storage area dividedinto blocks so that the semiconductor chip includes two banks.

[0025] Electric wires 15 (15 a and 15 b) electrically connected withboth of the first and second semiconductor storage parts 1 a and 1 b areprovided between the first and second semiconductor storage parts 1 aand 1 b. Whether or not to employ at least one of the first and secondsemiconductor storage parts 1 a and 1 b as a semiconductor memory devicecan be selected by changing the mode of the electric wires 15, i.e., bydisconnecting either one of the electric wires 15 or leaving all ofelectric wires 15.

[0026] The bare chip 1 according to this embodiment allows selection ofany of four cases, i.e., a case of employing both of the first andsecond semiconductor storage parts 1 a and 1 b, a case of employing onlythe second semiconductor storage part 1 b, a case of employing only thefirst semiconductor storage part 1 a and a case of employing neither thefirst semiconductor storage part 1 a nor the second semiconductorstorage part 1 b.

[0027] As shown in FIG. 2 along dicing lines (scribing lines), a region1 c formed with the electric wires 15 is provided between the first andsecond semiconductor storage parts 1 a and 1 b. Further, a plurality ofbonding pads 6 are provided on the central portion of the main surfaceof each of the first and second semiconductor storage parts 1 a and 1 b.Bonding wires 5 are connected to the plurality of bonding pads 6respectively. These bonding wires 5 are connected to bonding padsprovided on a module substrate 2 described later.

[0028] Each of the first and second semiconductor storage parts 1 a and1 b can singly operate as a semiconductor chip in response to signalsinput from the bonding pads 6 electrically connected thereto. In otherwords, all signals necessary for operating a single semiconductor chipare input through the bonding pads 6 electrically connected to the firstsemiconductor storage part 1 a, while all signals necessary foroperating a single semiconductor chip are also input through the bondingpads 6 electrically connected to the second semiconductor storage part 1b. In brief, each of the first and second semiconductor storage parts 1a and 1 b singly includes the bonding pads 6 capable of receiving allsignals required by each of the first and second semiconductor storageparts 1 a and 1 b for functioning as a single semiconductor chip.

[0029] As shown in FIG. 3, the electric wires 15 a and 15 b may bethick-film electric wires. Each of the thick-film electric wires 15 aand 15 b is connected to one of the bonding pads 6 of each of thesemiconductor storage parts 1 a and 1 b. In the region 1 c, an electricwire 16 is connected to a bonding pad 6.

[0030] When a plurality of such bare chips 1 a according to thisembodiment are mounted on the module substrate 2 as shown in FIG. 4, aspare semiconductor storage part 1 a or 1 b can be provided on themodule substrate 2. When the plurality of bare chips 1 mounted on themodule substrate 2 are thereafter subjected to a quality test and adefective bare chip 1 is detected, therefore, a spare bare chip 1 (thespare semiconductor storage part 1 a or 1 b) can substitute for thedefective bare chip 1 (the semiconductor storage part 1 a or 1 b).

[0031] Therefore, the semiconductor memory module according to thisembodiment shown in FIG. 4 can be subjected to a system test not onlyafter individual inspection of the bare chips 1 but also after mountingthe bare chips 1 on the module substrate 2, so that the semiconductormemory module can be repaired with the spare bare chip 1 when adefective bare chip 1 is detected.

[0032] As shown in FIG. 1, the electric wires 15 a and 15 b serving assemiconductor storage part selection circuits are provided on positionsfor dicing the semiconductor wafer 40 in general employment. Therefore,the semiconductor memory module according to this embodiment can befabricated without complicating a conventional dicing method.

[0033] The structure and effects of the semiconductor memory moduleaccording to this embodiment are now summarized.

[0034] The semiconductor memory module according to this embodiment isformed by mounting a plurality of bare chips 1 each serving as asemiconductor chip assembly including a plate semiconductor materialprepared by combining a plurality of semiconductor chips with each otheron the module substrate 2.

[0035] Each bare chip 1 includes the first and second semiconductorstorage parts 1 a and 1 b formed in the state of the wafer 40 serving asa semiconductor material for singly functioning as semiconductor chipsrespectively and the electric wires 15 each serving as a semiconductorstorage part employment/nonemployment selection circuit setting each ofthe first and second semiconductor storage parts 1 a and 1 b in either amode capable of inputting/outputting data or a mode incapable ofinputting/outputting data.

[0036] According to the aforementioned structure, the spare bare chip 1is provided among the plurality of bare chips 1, to attain the followingeffects:

[0037] In the stage of the semiconductor memory module obtained bymounting the plurality of bare chips 1 including the spare bare chip 1on the module substrate 2, each of the plurality of bare chips 1including the spare bare chip 1 is in a mode capable ofinputting/outputting data. In this state, therefore, the semiconductormemory module cannot exhibit a proper function.

[0038] Therefore, the spare bare chip 1 included in the plurality ofbare chips 1 must be set in a mode incapable of inputting/outputtingdata. In a step of fabricating the semiconductor memory module, a systemtest must be performed for checking whether or not each of the pluralityof bare chips 1 properly functions after mounting the plurality of barechips 1 on the module substrate 2.

[0039] If no defective bare chip 1 is detected among the plurality ofbare chips 1 in the aforementioned system test on the semiconductormemory module according to this embodiment, the spare semiconductorstorage part 1 a or 1 b can be brought into an unused state through theaforementioned electric wire 15 a or 15 b serving as a semiconductorstorage part employment/nonemployment selection circuit.

[0040] When a defective bare chip 1 (semiconductor storage part 1 a or 1b) is detected among the plurality of bare chips 1, the defective barechip 1 (semiconductor storage part 1 a or 1 b) can be brought into anunused state incapable of inputting/outputting data through theaforementioned electric wire 15 a or 15 b while keeping the sparesemiconductor storage part 1 a or 1 b in a used state capable ofinputting/outputting data.

[0041] Consequently, the semiconductor memory module can exhibit aprescribed function whether or not the plurality of bare chips 1 mountedon the module substrate 2 include a defective bare chip 1. Thus, theyield of the semiconductor memory module is improved.

[0042] The electric wires 15 a and 15 b serving as semiconductor storagepart employment/nonemployment selection circuits are provided on theregion 1 c between the semiconductor storage parts 1 a and 1 b.Therefore, the space of the wafer 40 serving as the semiconductormaterial can be effectively utilized.

[0043] The electric wires 15 include the electric wires 15 a and 15 belectrically connected to the first and second semiconductor storageparts 1 a and 1 b respectively, so that the first and secondsemiconductor storage parts 1 a and 1 b enter the mode incapable ofinputting/outputting data when the electric wires 15 a and 15 b aredisconnected. Therefore, used and unused states of the bare chip 1 canbe selected by simply disconnecting at least one of the electric wires15 a and 15 b.

[0044] In the semiconductor memory module according to this embodiment,the semiconductor storage part employment/nonemployment selectioncircuits are mounted on unused dicing lines of a conventional productwithout changing the shot layout of the conventional product shown inFIG. 5, whereby the aforementioned effects can be attained whilepartially utilizing the mode of the conventional product and aconventional dicing technique.

[0045] A method of fabricating the bare chip 1 according to thisembodiment includes steps of forming a single wafer 40, forming thefirst and second semiconductor storage parts 1 a and 1 b capable ofstoring data independently of each other while forming a dicing region 1c having a width substantially equivalent to the width of the blade of adicing machine between the first and second semiconductor storage parts1 a and 1 b and dicing the wafer 40 along the dicing region 1 c forseparating the first and second semiconductor storage parts 1 a and 1 bfrom each other.

[0046] The method of fabricating the bare chip 1 according to thisembodiment includes a step of forming the electric wires 15 a and 15 beach serving as a semiconductor storage part employment/nonemploymentselection circuit capable of setting each of the first and secondsemiconductor storage parts 1 a and 1 b in either a mode capable ofinputting/outputting data or a mode incapable of inputting/outputtingdata on each region 1 c between the first and second semiconductorstorage parts 1 a and 1 b. The method also includes a step of dicing thewafer 40 along the region 1 c for separating the first and secondsemiconductor storage parts 1 a and 1 b from each other.

[0047] According to the aforementioned method, the wafer 40 can be dicedby the existing dicing method, while the electric wires 15 a and 15 bcan be effectively provided on a region not subjected to dicing.

[0048] In the method of fabricating the bare chip 1 according to thisembodiment, the electric wires 15 a and 15 b are electrically connectedto the first and second semiconductor storage parts 1 a and 1 b in thestage partially forming the single semiconductor wafer 40 respectively.

[0049] According to the aforementioned method, the electric wires 15 aand 15 b can be more readily electrically connected to the first andsecond semiconductor storage parts 1 a and 1 b respectively.

[0050] While the semiconductor memory module according to thisembodiment has been described with reference to the semiconductor chiphaving two semiconductor storage parts, i.e., the first and secondsemiconductor storage parts 1 a and 1 b, the number of the semiconductorstorage parts is not restricted to two so far as disconnectable electricwires are connected to the semiconductor storage parts respectively.

[0051] Further, the semiconductor storage part employment/nonemploymentselection circuits, described with reference to the electric wires 15 aand 15 b, may alternatively be formed by other circuits so far as eachof the circuits can switch any of a plurality of semiconductor storageparts or each an arbitrary combination of semiconductor storage partsbetween a usable state and an unusable state.

[0052] Although the present invention has been described and illustratedin detail, it is clearly understood that the same is by way ofillustration and example only and is not to be taken by way oflimitation, the spirit and scope of the present invention being limitedonly by the terms of the appended claims.

What is claimed is:
 1. A semiconductor memory module having a pluralityof semiconductor chip assemblies, each including a plate semiconductormaterial formed by combining a plurality of semiconductor chips witheach other, mounted on a module substrate, wherein each saidsemiconductor chip assembly includes: a plurality of semiconductorstorage parts provided on said semiconductor material for individuallyfunctioning as said plurality of semiconductor chips, and asemiconductor storage part employment/nonemployment selection circuitsetting each of said plurality of semiconductor storage parts in eithera mode capable of inputting/outputting data or a mode incapable ofinputting/outputting said data.
 2. The semiconductor memory moduleaccording to claim 1, wherein said semiconductor storage partemployment/nonemployment selection circuit is provided on a regionbetween said semiconductor storage parts.
 3. The semiconductor memorymodule according to claim 1, wherein said semiconductor storage partemployment/nonemployment selection circuit includes an electric wireelectrically connected to said plurality of semiconductor storage partsrespectively for setting each of said plurality of semiconductor storageparts in said mode incapable of inputting/outputting said data bydisconnecting said electric wire.
 4. The semiconductor memory moduleaccording to claim 1, wherein said electric wire is provided on saidsemiconductor material.